Silicon dioxide has typically been used as the dielectric material between the electrically conductive gate electrode, often formed of polysilicon, and the semiconducting channel of a transistor, which is typically formed of silicon. Silicon dioxide has provided adequately high capacitance for gate insulation in the past, with devices having gate geometries of about 130 nanometers and greater. However, with the ever increasing demands of scaled-down device geometries and more densely populated integrated circuits, silicon oxide tends to no longer be good enough for the gate insulation layer.
Current transistor geometries use a gate insulation layer of silicon dioxide that is about twelve to sixteen angstroms thick, or the thickness of about six to ten individual silicon atoms. The silicon dioxide layer gates the electrons through the channel, controlling the flow of electricity across the transistor. However, when the transistor is reduced in size, the silicon dioxide gate insulation layer is also proportionally thinned. As gate lengths decrease from one hundred and thirty nanometers to ninety, sixty-five, and even thirty nanometers, the thickness of the silicon oxide gate will be reduced to less than ten angstroms, or to about three monolayers.
Unfortunately, once the gate insulation layer is reduced to less than about twenty angstroms, the silicon dioxide is no longer able to provide effective insulation from the effects of quantum tunneling currents, and the transistor tends to exhibit relatively high leakage.
Thus, the integrated circuit fabrication industry is searching for gate insulator materials with a low equivalent oxide thickness that mimics the electrical properties of very thin silicon dioxide, while providing a thicker physical layer over the channel to prevent quantum-mechanical tunneling. New materials in the form of oxides of heavy and rare earth metals, with higher dielectric constants and higher capacitances have been investigated with some promising results, including HfSiON, ZrO2, HfO2, HfON, La2O3, CeO2, Na2O3, Sm2O3, Eu2O3, Gd2O3, Tb2O3, Dy2O3, Ho2O3, Er2O3, Tm2O3, Yb2O3, Lu2O3. 
However, these so-called high k materials have other problems associated with their use. For example, they do not easily form volatile compounds and are relatively difficult to remove by either dry etching or wet etching. Dry etching has been attempted with ion milling or bombardment and sputtering with the use of argon or other inert ions. However, the process is time consuming and can cause extensive damage to the surrounding structures, such as the polysilicon gate electrode. The necessarily extended use of plasma as an etch tends to increase the plasma damage to the substrate itself, as well as to other structures.
There is a need, therefore, for a method whereby such high k materials can be patterned and etched without unduly damaging the surrounding structures that are formed in a conventional CMOS process flow.